1. Field of Invention
The present invention relates to a delay locked loop. More particularly, the present invention relates to a delay locked loop circuit for preventing harmonic lock and phase ambiguity.
2. Description of Related Art
Delay locked loops are often used in communication/information systems as clock control circuits for synchronizing the output signal with the internal reference clock of the circuit or to keep a fixed phase delay between the two. Delay locked loops are also used as signal clock synchronous circuits because of low phase jitter.
A conventional delay locked loop circuit generally comprises four units: a phase detector, a charge pump, a loop filter, and a delay unit. The delay unit receives a reference signal and generates an output signal. Since the delay circuit delays the signal transferred therein, there is a phase difference between the output signal and the reference signal. The phase detector detects the phase difference and allows the charge pump to generate a phase control voltage, and the phase control voltage is transmitted to the delay unit through the loop filter. The delay time of the output signal is adjusted by changing the voltage level of the phase control voltage to synchronize the output signal with the reference signal or to keep a fixed phase difference between the output signal and the reference signal.
In the conventional design of the delay locked loop circuits, harmonic lock and phase ambiguity are two common problems. Harmonic lock occurs when the frequency of the output signal is integral multiple of the frequency of the reference signal, the rising edges of the output signal and the reference signal appear at the time, and then the delay locked loop mistakenly determines that the output signal is synchronous with the reference signal. Phase ambiguity occurs when the delay locked loop can not determine the phase difference between the output signal and the reference signal correctly. The delay locked loop cannot lock the output signal correctly when the delay time of the output signal is less than ½ clock cycle or greater than 3/2 clock cycle, so that the output signal cannot be synchronized with the reference signal.
A delay locked circuit with phase discriminator has been disclosed for reducing the occurrence of harmonic lock by multiple delay point discrimination. However, the area cost of the chip will be too high since the circuit of the phase discriminator is too large even though the accuracy of phase discrimination can be increased.
A multiple-phases delay locked circuit has been disclosed for reducing the occurrence of harmonic lock by an additional harmonic lock preventing unit. However, since the harmonic lock preventing unit is formed by a plurality of phase detectors, the implementation thereof also takes a large chip area.
Moreover, the present delay locked circuits also have the disadvantage of small operation range. Thus, a delay locked circuit, which can prevent harmonic lock and has large operation range, and the method thereof are required.